The present invention relates generally to phase startable clock devices and more particularly to a phase startable clock device having improved stability.
In a high speed digitizing instrument, an analog input signal is sampled and quantized during an acquisition interval under control of a sampling strobe signal. The sampling strobe signal may be, or may be derived from, a high frequency sinusoidal signal. It may be desired that the high frequency sinusoidal signal start with a known phase at a fixed time following a control signal transition that is representative of a trigger event. It is known to generate such a high frequency sinusoidal signal using a circuit known as a phase startable clock.
U.S. Pat. No. 5,402,019 describes a phase startable clock device having improved jitter performance and minimal start-up time delay. FIG. 1 shows a generalized form of the phase startable clock device 10 having a stable oscillator 12 generating a sinusoidal signal. The sinusoidal signal is applied to phase splitters 14 and 16. The phase splitters 14 and 16 have gains A and B and phases xcex1 and xcex2 and shift the phases of the sinusoidal input signals relative to each other. Generally in a two phase splitter device, the sinusoidal signals are in quadrature phase or 90xc2x0 apart. Matching of the gains A and B and having an exact quadrature relationship between the sinusoidal signals are not critical for operation of the device. Each phase shifted sinusoidal signal from the phase splitters 14 and 16 is coupled to a respective multiplier 18, 20 and track-and-hold circuit 22, 24. A control transition signal from a control signal source 26 in the form of a trigger signal is applied to each track-and-hold 22, 24. The held phase values on the respective track-and-hold circuits 22 and 24 are cross-coupled to the multipliers 20 and 18. The outputs of the multipliers 18 and 20 are summed in summing circuit 28 to generate an output signal with a predetermined phase at a predetermined time relative to the transition.
In operation, the phase startable clock device generates a constant value at the output from the summing circuit 28 when the track-and-hold circuits 22 and 24 are tracking the phase shifted sinusoidal signals of the oscillator 12. When a trigger transition occurs, the track-and-hold circuits 22 and 24 hold the phase values of the phase shifted sinusoidal signals. The phase values captured at the time of the trigger event are applied to the multipliers 18 and 20 which generate weighted sinusoidal signals based on these phase values. The weighted sinusoidal signals are added together in the summing circuit to produce the output signal whose phase is constant with respect to the trigger event. The output of the phase startable clock device is used as a coarse time delay for a strobe generator (not shown) to generate a strobe pulse that is applied to a sampler circuit to sample an input signal under test at an instant in time.
Gain, offset and leakage errors in the track-and-hold circuits 22 and 24 cause the held phase values to vary over time. This alters the phase-time relationship of the output signal relative to the transition. As a result, the coarse time delay for the strobe generator will vary producing timing errors in the resultant strobe pulses to the sampler. What is needed is a phase startable clock device that maintains the desired phase-time relationship to a transition signal resulting in a stable clock output.
Accordingly, the present invention is to an apparatus for generating a phase stable clock signal having at least first and second track-and-hold circuits, first and second multiplexers and an infinite track-and hold circuit. The track-and-hold circuits and the multiplexer are incorporated into a phase gate that further include at least first and second multipliers. The track-and hold circuits and the multipliers are coupled to receive respective phase shifted continuous sinusoidal signals. The track-and-hold circuits are coupled to receive a control input signal having a transition between a first state and a second state to capture and hold the respective phase values of the sinusoidal signals. The infinite track-and hold circuit is coupled to receive the phase values from track-and-hold circuits and generates replicas of the phase values. Each multiplexer is coupled to receive the phase value held on one of the track-and-hold circuits and the corresponding replica phase value from the infinite track-and-hold circuit. The multiplexers selectively couple to phase values to the multipliers during a first time period and the replica phase values during a second time period. A summing circuit is coupled to receive respective output signals from the multipliers to generate an output signal with a predetermined startup phase relative to the transition.
The infinite track-and-hold includes at least first and second analog-to-digital converters that are respectively coupled to corresponding first and second digital-to-analog converters. Each analog-to-digital converter is coupled to receive one of the phase values at the output of the first and second track-and-hold circuits and generates a digital value representative of that phase value. Each digital-to-analog converter is coupled to receive one of the digital values from the analog-to-digital converters and generates a replica analog phase value. The apparatus further includes a phase splitter receiving a continuous sinusoidal signal and generating the phase shifted continuous sinusoidal signals. At least first and second summing circuits may be coupled to the respective outputs of the track-and-hold circuits with each summing circuit being coupled to receive an offset correction value. Each of the first and second multipliers, which are preferably four quadrant multipliers, may be coupled to receive a gain control value. The first time period in which the multiplexers couple the track-and-hold phase values to the multipliers is in the range of 10 microseconds. The second time period in which the multiplexers couple the infinite track-and-hold phase values to the multipliers is in the range of greater than 10 microseconds.
The preferred implementation of the apparatus includes a phase splitter coupled to receive the continuous sinusoidal signal and generates first, second, and third phase shifted continuous sinusoidal signals a(t), b(t), and c(t) of predetermined phases. A third track-and-hold circuit is coupled to receive the third phase shifted sinusoidal signal c(t) with the first and second track-and-hold circuits respectively coupled to receive the first and second phase shifted sinusoidal signals a(t) and b(t). The third track-and-hold circuits also receives the control input signal to capture and hold the phase value of the third phase shifted sinusoidal signal. The infinite track-and-hold circuit receives the phase value on the third track-and-hold circuit and generates a replica of that phase value as well. A third multiplexer is coupled to receive the phase value held on the third track-and-hold circuit and the replica phase value from the infinite track-and-hold circuit. The third multiplexer selectively couples the phase value to the third multiplier during a first time period and the replica phase value during a second time period. The first multiplier multiplies the first phase shifted sinusoidal by b(T)xe2x88x92c(T) to produce a first product signal, the second multiplier multiplies the second phase shifted sinusoidal by c(T)xe2x88x92a(T) to produce a second product signal and the third multiplier multiplies the third phase shifted sinusoidal signal by a(T)xe2x88x92b(T) to produce a third product signal. The summing circuit receives the respective product signals from the multipliers to generate the output signal wherein a(T), b(T) and c(T) are the values of the first, second and third phase shifted sinusoidal signals at the time of the transition. The predetermined phases are preferably of the first, second and third phase shifted sinusoidal signals are 0xc2x0, 120xc2x0, and 240xc2x0 respectively.
The objects, advantages and novel features of the present invention are apparent from the following detailed description when read in conjunction with the appended claims and attached drawings.